AMD Duron 1.3GHz - Mainstream Muscle

Author :Wayne Date : 21st January 2002

3DVelocity would like to thank AMD and especially Theresa Zimmer for their help and courtesy in providing this processor for review.

Power management :

The other problem that arises from the switch to 1.75 concerns one of the Duron's most obvious target markets, the laptop user. In order to preserve battery life and also control temperatures, AMD incorporate a range of power saving features into the Duron. The AMD Duron processor model 7 supports low-power Halt and Stop Grant states. These states are used by Advanced
Configuration and Power Interface (ACPI) enabled operating systems for processor power management. below is AMD's description of what each of the states means, it's a bit long winded so if you're not feeling particularly technically minded just skip over it.

Working State The Working state is the state in which the processor is executing instructions.

Halt State When the processor executes the HLT instruction, the processor enters the Halt state and issues a Halt special cycle to the AMD Duron system bus. The processor only enters the low power state dictated by the CLK_Ctl MSR if the system controller (Northbridge) disconnects the AMD Duron system bus in response to the Halt special cycle. If STPCLK# is asserted, the processor will exit the Halt state and enter the Stop Grant state. The processor will initiate a system bus connect, if it is disconnected, then issue a Stop Grant special cycle. When STPCLK# is deasserted, the processor will exit the Stop Grant state and re-enter the Halt state. The processor will issue a Halt special cycle when re-entering the Halt state. The Halt state is exited when the processor detects the assertion of INIT#, RESET#, SMI#, or an interrupt via the INTR or NMI pins, or via a local APIC interrupt message. When the Halt state is exited, the processor will initiate an AMD Duron system bus connect if it is disconnected.

Stop Grant States The processor enters the Stop Grant state upon recognition of assertion of STPCLK# input. After entering the Stop Grant state, the processor issues a Stop Grant special bus cycle on the AMD Duron system bus. The processor is not in a low-power state at this time, because the AMD Duron system bus is still connected. After the Northbridge disconnects the AMD Duron system bus in response to the Stop Grant special bus cycle, the processor enters a low-power state dictated by the CLK_Ctl MSR. If the Northbridge needs to probe the processor during the Stop Grant state while the system bus is disconnected, it must first connect the system bus. Connecting the system bus places the processor into the higher power probe state. After the Northbridge has completed all probes of the processor, the Northbridge must disconnect the AMD Duron system bus again so that the processor can return to the low-power state. During the Stop Grant states, the processor latches INIT#, INTR, NMI, SMI#, or a local APIC interrupt message, if they are asserted. The Stop Grant state is exited upon the deassertion of STPCLK# or the assertion of RESET#. When STPCLK# is deasserted, the processor initiates a connect of the AMD Duron system bus if it is disconnected. After the processor enters the Working state, any pending interrupts are recognized and serviced and the processor resumes execution at the instruction boundary where STPCLK# was initially recognized. If RESET# is sampled asserted during the Stop Grant state, the processor exits the Stop Grant state and the reset process begins. There are two mechanisms for asserting STPCLK#—hardware and software. The Southbridge can force STPCLK# assertion for throttling to protect the processor from exceeding its maximum case temperature. This is accomplished by asserting the THERM# input to the Southbridge. Throttling asserts STPCLK# for a percentage of a predefined throttling period: STPCLK# is repetitively asserted and deasserted until THERM# is deasserted. Software can force the processor into the Stop Grant state by accessing ACPI-defined registers typically located in the Southbridge. The operating system places the processor into the C2 Stop Grant state by reading the P_LVL2 register in the Southbridge. If an ACPI Thermal Zone is defined for the processor, the operating system can initiate throttling with STPCLK# using the ACPI defined P_CNT register in the Southbridge. The
Northbridge connects the AMD Duron system bus, and the processor enters the Probe state to service cache snoops during Stop Grant for C2 or throttling. In C2, probes are allowed. The Stop Grant state is also entered for the S1, Powered On Suspend, system sleep state based on a write to the SLP_TYP and SLP_EN fields in the ACPI-defined Power Management 1 control register in the Southbridge. During the S1 Sleep state, system software ensures no bus master or probe activity occurs. The Southbridge deasserts STPCLK# and brings the processor out of the S1 Stop Grant state when any enabled resume event occurs.

Probe State The Probe state is entered when the Northbridge connects the AMD Duron system bus to probe the processor (for example, to snoop the processor caches) when the processor is in the Halt or Stop Grant state. When in the Probe state, the processor responds to a probe cycle in the same manner as when it is in the Working state. When the probe has been serviced, the processor returns to the same state as when it entered the Probe state (Halt or Stop Grant state). When probe activity is completed the processor only returns to a low-power state after the Northbridge disconnects the AMD Duron system bus again.

 

Page 4- Processor details

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