AMD Athlon XP 2000+, A Virtual Milestone!

Author : Wayne Date : 7th January 2002

3DVelocity would like to thank AMD and especially Theresa Zimmer for their help and courtesy in providing this processor for review. .

 

 

Technology Overview :

The whole premise of the Athlon XP is family is what AMD have termed "Quantispeed Architecture" AMD want this to become the buzz phrase that people refer to when they think of the AthlonXP and it isn't just a single technology but rather a collection of enhancements created to drive the XP to new heights. For reference, the Athlon XP family now looks like this :

Model Number	Operating Frequency
2000+	1.67GHz
1900+	1.60GHz
1800+	1.53GHz
1700+	1.47GHz
1600+	1.40GHz
1500+	1.33GHz

So, what exactly is Quantispeed Architecture? Here's the recipe :

• Nine-issue superpipelined, superscalar x86 processor microarchitecture designed for high performance
• Multiple parallel x86 instruction decoders
• Three out-of-order, superscalar, fully pipelined floating point execution units, which execute x87 (floating point), MMX and 3DNow! instructions
• Three out-of-order, superscalar, pipelined integer units
• Three out-of-order, superscalar, pipelined address calculation units
• 72-entry instruction control unit
• Advanced hardware data prefetch
• Exclusive and speculative Translation Look-aside Buffers
• Advanced dynamic branch prediction

Impressive eh? Now let's look at the key advancements -

Nine-issue, superscalar, fully pipelined micro-architecture

To keep it simple, these pipelines are used to feed data from the application to the execution engines. The depth of these pipelines dictates not only the maximum core frequency but also the IPC (amount of work done in a single clock cycle - we'll be looking at this later). Deep pipelines allow for higher frequencies but result in a lower IPC while shorter pipelines do exactly the opposite, pegging frequecies to lower levels but allowing for more operations to be carried out per clock cycle. By carefully balancing pipeline depth, the AthlonXP is able to deliver a compromise between IPC and frequency that offers the best all-round solution.

Superscalar, fully pipelined Floating Point Unit (FPU)

Once considered an AMD weakness, the XP's current floating point unit is widely recognised as the most able in the business. The XP boasts three out-of-order, superscalar, fully pipelined floating point execution units which also handle MMX and 3DNow! instructions.

Hardware data prefetch

Not exactly a new technology, the idea is that data is shifted from system memory to the processor's Level 1 Instruction Cache. Because L1 cache is so much faster than system memory, critical data is available to the execution units much faster than would be the case otherwise. The resultant increase in efficiency means applications run faster and smoother.

Exclusive and speculative Translation Look-aside Buffers (TLBs)

Or "associative registers" as they're sometimes known are essentially data maps that are stored close to the processor. Just as a road map can help you shorten journey times, so these data maps help keep track of critical data to prevent the CPU from stalling while waiting for data. AMD have made these buffers larger for the Athlon XP meaning more data can be tracked. Also, the fact that these buffers are used solely for this task means data isn't duplicated needlessly also adding to overall efficiency and a higher IPC. The speculative part simply means that future data maps can be created quickly and speculatively based on the current data stream.

Other Specs :

3DNow! Professional technology for leading-edge 3D operation

Page 4 - IPC and Performance Ratings